Unified Video Decoder

Unified Video Decoder (UVD), previously called Universal Video Decoder, is the name given to AMD's dedicated video decoding ASIC. There are multiple versions implementing a multitude of video codecs, such as H.264 and VC-1.

UVD was introduced with the Radeon HD 2000 Series and is integrated into some of the AMD GPUs and APUs. UVD occupies a considerable amount of the die surface[1] and is not to be confused with AMD's Video Coding Engine (VCE).

OverviewEdit

The UVD is based on an ATI Xilleon video processor, which is incorporated onto the same die as the GPU and is part of the ATI Avivo HD for hardware video decoding, along with the Advanced Video Processor (AVP). UVD, as stated by AMD, handles decoding of H.264/AVC, and VC-1 video codecs entirely in hardware.

The UVD technology is based on the Cadence Tensilica Xtensa[2] processor,[3][4][5] which was originally licensed by ATI Technologies Inc. in 2004.[6]

UVD/UVD+Edit

In early versions of UVD, video post-processing is passed to the pixel shaders and OpenCL kernels. MPEG-2 decoding is not performed within UVD, but in the shader processors. The decoder meets the performance and profile requirements of Blu-ray and HD DVD, decoding H.264 bitstreams up to a bitrate of 40 Mbit/s. It has context-adaptive binary arithmetic coding (CABAC) support for H.264/AVC.

Unlike video acceleration blocks in previous generation GPUs, which demanded considerable host-CPU involvement, UVD offloads the entire video-decoder process for VC-1 and H.264 except for video post-processing, which is offloaded to the shaders. MPEG-2 decode is also supported, but the bitstream/entropy decode is not performed for MPEG-2 video in hardware.

Previously, neither ATI Radeon R520 series' ATI Avivo nor NVidia Geforce 7 series' PureVideo assisted front-end bitstream/entropy decompression in VC-1 and H.264 - the host CPU performed this work.[7] UVD handles VLC/CAVLC/CABAC, frequency transform, pixel prediction and inloop deblocking, but passes the post processing to the shaders.[8] Post-processing includes denoising, de-interlacing, and scaling/resizing. AMD has also stated that the UVD component being incorporated into the GPU core only occupies 4.7 mm² in area on 65 nm fabrication process node.

A variation on UVD, called UVD+, was introduced with the Radeon HD 3000 series. UVD+ support HDCP for higher resolution video streams.[9] But UVD+ was also being marketed as simply UVD.

UVD 2Edit

The UVD saw a refresh with the release of the Radeon HD 4000 series products. The UVD 2 features full bitstream decoding of H.264/MPEG-4 AVC, VC-1, as well as iDCT level acceleration of MPEG2 video streams. Performance improvements allow dual video stream decoding and Picture-in-Picture mode. This makes UVD2 full BD-Live compliant.

The UVD 2.2 features a re-designed local memory interface and enhances the compatibility with MPEG2/H.264/VC-1 videos. However, it was marketed under the same alias as "UVD 2 Enhanced" as the "special core-logic, available in RV770 and RV730 series of GPUs, for hardware decoding of MPEG2, H.264 and VC-1 video with dual-stream decoding". The nature of UVD 2.2 being an incremental update to the UVD 2 can be accounted for this move.

UVD 3Edit

UVD 3 adds support for additional hardware MPEG2 decoding (entropy decode), DivX and Xvid via MPEG-4 Part 2 decoding (entropy decode, inverse transform, motion compensation) and Blu-ray 3D via MVC (entropy decode, inverse transform, motion compensation, in-loop deblocking).[10][11] along with 120 Hz stereo 3D support,[12] and is optimized to utilize less CPU processing power. UVD 3 also adds support for Blu-ray 3D stereoscopic displays.[citation needed]

UVD 4Edit

UVD 4 includes improved frame interpolation with H.264 decoder.[13] UVD 4.2 was introduced with the AMD Radeon Rx 200 series and Kaveri APU."X.ORG Radeon UVD (Unified Video Decoder) Hardware-UVD4.2: KAVERI, KABINI, MULLINS, BONAIRE, HAWAII". May 2016.

UVD 5Edit

UVD 5 was introduced with the AMD Radeon R9 285. New to UVD is full support for 4K H.264 video, up to level 5.2 (4Kp60).[14]

UVD 6Edit

The UVD 6.0 decoder and Video Coding Engine 3.1 encoder were reported to be first used in GPUs based on GCN 3, including Radeon R9 Fury series and "Carrizo"-APUs,[15][16] followed by AMD Radeon Rx 300 Series (Pirate Islands GPU family) and AMD Radeon Rx 400 Series (Arctic Islands GPU family).[17] The UVD version in "Fiji" and "Carrizo"-based graphics controller hardware is also announced to provide support for High Efficiency Video Coding (HEVC, H.265) hardware video decoding, up to 4K, 8-bits color (H.265 version 1, main profile);[18][19][20] and there is support for the 10bit-color HDR both H.265 and VP9 video codec in the AMD Radeon 400 series with UVD 6.3.[21][22][23]

UVD 7Edit

The UVD 7.0 decoder and Video Coding Engine 4.0 encoder are included in the Vega-based GPUs.[24][25] But there is still no fixed function VP9 hardware decoding.[26]

UVD 7.2Edit

AMD's Vega20 GPU, present in the Instinct Mi50, Instinct Mi60 and Radeon VII cards, include VCE 4.1 and two UVD 7.2 instances.[27][28]

VCN 1Edit

Starting with the integrated graphics of the Raven Ridge APU (Ryzen 2200/2400G), the former UVD and VCE have been replaced by the new "Video Core Next" (VCN). VCN 1.0 adds full hardware decoding for the VP9 codec. [29]

Format supportEdit

[30][29]

Unified Video Decoder and Video Core Next decoding/encoding support[30][29]
Implementation H.262 (MPEG-2) MPEG-4 VC-1/ WMV 9 H.264 (MPEG-4 AVC) H.265 (HEVC) VP9 JPEG 4K 10 bit AMD Fluid Motion
Decoding Decoding Decoding Decoding Encoding Decoding Encoding Decoding Decoding Frame interpolation
UVD 1.0 RV610, RV630, RV670, RV620, RV635 No No Yes Yes No No No No No 2K 8-bit No
UVD 2.0 RS780, RS880, RV770
UVD 2.2 RV710, RV730, RV740
UVD 2.3 Cedar, Redwood, Juniper, Cypress
UVD 3.0 Palm (Wrestler/Ontario), Sumo (Llano), Sumo2 (Llano) Yes Yes
UVD 3.1 Barts, Turks, Caicos, Cayman
UVD 3.2 Aruba (Trinity/Richland), Tahiti VCE[A]
UVD 4.0 Cape Verde, Pitcairn, Oland Yes
UVD 4.2 Kaveri, Kabini, Mullins, Bonaire, Hawaii
UVD 5.0 Tonga Yes
UVD 6.0 Carrizo, Fiji Yes Yes
UVD 6.2 Stoney Yes
UVD 6.3 Polaris, VegaM Yes
UVD 7.0 Vega10, Vega12
UVD 7.2 Vega20
VCN 1.0 Raven Yes No
VCN 2.0 Navi10, Navi14
Implementation Decoding Decoding Decoding Decoding Encoding Decoding Encoding Decoding Decoding 4K 10 bit Frame interpolation
H.262 (MPEG-2) MPEG-4 VC-1/ WMV 9 H.264 (MPEG-4 AVC) H.265 (HEVC) VP9 JPEG AMD Fluid Motion
  1. ^ MPEG-4 AVC encoding by separate Video Coding Engine

AvailabilityEdit

Most of the Radeon HD 2000 series video cards implement the UVD for hardware decoding of 1080p high definition contents.[31] However, the Radeon HD 2900 series video cards do not include the UVD (though it is able to provide partial functionality through the use of its shaders), which was incorrectly stated to be present on the product pages and package boxes of the add-in partners' products before the launch of the Radeon HD 2900 XT,[citation needed] either stating the card as featuring ATI Avivo HD or explicitly UVD,[citation needed] which only the former statement of ATI Avivo HD is correct. The exclusion of UVD was also confirmed by AMD officials.[32]

UVD2 is implemented in the Radeon RV7x0 and R7x0 series GPUs. This also includes the RS7x0 series used for the AMD 700 chipset series IGP motherboards.

Feature overviewEdit

APUsEdit

The following table shows features of AMD's APUs (see also: List of AMD accelerated processing units).

Codename Server Basic Toronto
Micro Kyoto
Desktop Mainstream Carrizo Bristol Ridge Raven Ridge Picasso Renoir
Entry Llano Trinity Richland Kaveri
Basic Kabini
Mobile Performance Renoir
Mainstream Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Picasso
Entry Dalí
Basic Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge
Embedded Trinity Bald Eagle Merlin Falcon,
Brown Falcon
Great Horned Owl Ontario, Zacate Kabini Steppe Eagle, Crowned Eagle,
LX-Family
Prairie Falcon Banded Kestrel
Platform High, standard and low power Low and ultra-low power
Released Aug 2011 Oct 2012 Jun 2013 Jan 2014 Jun 2015 Jun 2016 Oct 2017 Jan 2019 Mar 2020 Jan 2011 May 2013 Apr 2014 May 2015 Feb 2016 Apr 2019
CPU microarchitecture K10 Piledriver Steamroller Excavator "Excavator+"[33] Zen Zen+ Zen 2 Bobcat Jaguar Puma Puma+[34] "Excavator+" Zen
ISA x86-64 x86-64
Socket Desktop High-end N/A N/A
Mainstream N/A AM4
Entry FM1 FM2 FM2+[a] N/A
Basic N/A N/A AM1 N/A
Other FS1 FS1+, FP2 FP3 FP4 FP5 FP6 FT1 FT3 FT3b FP4 FP5
PCI Express version 2.0 3.0 4.0 2.0 3.0
Fab. (nm) GF 32SHP
(HKMG SOI)
GF 28SHP
(HKMG bulk)
GF 14LPP
(FinFET bulk)
GF 12LP
(FinFET bulk)
TSMC N7
(FinFET bulk)
TSMC N40
(bulk)
TSMC N28
(HKMG bulk)
GF 28SHP
(HKMG bulk)
GF 14LPP
(FinFET bulk)
Die area (mm2) 228 246 245 245 250 210[35] 156 75 (+ 28 FCH) 107 ? 125 149
Min TDP (W) 35 17 12 10 4.5 4 3.95 10 6
Max APU TDP (W) 100 95 65 18 25
Max stock APU base clock (GHz) 3 3.8 4.1 3.7 3.8 3.6 3.7 3.8 1.75 2.2 2 2.2 3.2 3.3
Max APUs per node[b] 1 1
Max CPU[c] cores per APU 4 8 2 4 2
Max threads per CPU core 1 2 1 2
Integer structure 3+3 2+2 4+2 4+2+1 1+1+1+1 2+2 4+2
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF    
IOMMU[d] N/A  
BMI1, AES-NI, CLMUL, and F16C N/A  
MOVBE N/A  
AVIC, BMI2 and RDRAND N/A  
ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERO N/A   N/A  
WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMIT N/A   N/A
FPUs per core 1 0.5 1 1 0.5 1
Pipes per FPU 2 2
FPU pipe width 128-bit 256-bit 80-bit 128-bit
CPU instruction set SIMD level SSE4a[e] AVX AVX2 SSSE3 AVX AVX2
3DNow! 3DNow!+ N/A N/A
PREFETCH/PREFETCHW    
FMA4, LWP, TBM, and XOP N/A   N/A N/A   N/A
FMA3    
L1 data cache per core (KiB) 64 16 32 32
L1 data cache associativity (ways) 2 4 8 8
L1 instruction caches per core 1 0.5 1 1 0.5 1
Max APU total L1 instruction cache (KiB) 256 128 192 256 512 64 128 96 128
L1 instruction cache associativity (ways) 2 3 4 8 2 3 4
L2 caches per core 1 0.5 1 1 0.5 1
Max APU total L2 cache (MiB) 4 2 4 1 2 1
L2 cache associativity (ways) 16 8 16 8
APU total L3 cache (MiB) N/A 4 8 N/A 4
APU L3 cache associativity (ways) 16 16
L3 cache scheme Victim N/A Victim Victim
Max stock DRAM support DDR3-1866 DDR3-2133 DDR3-2133, DDR4-2400 DDR4-2400 DDR4-2933 DDR4-3200, LPDDR4-4266 DDR3L-1333 DDR3L-1600 DDR3L-1866 DDR3-1866, DDR4-2400 DDR4-2400
Max DRAM channels per APU 2 1 2
Max stock DRAM bandwidth (GB/s) per APU 29.866 34.132 38.400 46.932 68.256 10.666 12.800 14.933 19.200 38.400
GPU microarchitecture TeraScale 2 (VLIW5) TeraScale 3 (VLIW4) GCN 2nd gen GCN 3rd gen GCN 5th gen[36] TeraScale 2 (VLIW5) GCN 2nd gen GCN 3rd gen[36] GCN 5th gen
GPU instruction set TeraScale instruction set GCN instruction set TeraScale instruction set GCN instruction set
Max stock GPU base clock (MHz) 600 800 844 866 1108 1250 1400 2100 538 600 ? 847 900 1200
Max stock GPU base GFLOPS[f] 480 614.4 648.1 886.7 1134.5 1760 1971.2 2150.4 86 ? ? ? 345.6 460.8
3D engine[g] Up to 400:20:8 Up to 384:24:6 Up to 512:32:8 Up to 704:44:16[37] Up to 512:?:? 80:8:4 128:8:4 Up to 192:?:? Up to 192:?:?
IOMMUv1 IOMMUv2 IOMMUv1 ? IOMMUv2
Video decoder UVD 3.0 UVD 4.2 UVD 6.0 VCN 1.0[38] UVD 3.0 UVD 4.0 UVD 4.2 UVD 6.0 UVD 6.3 VCN 1.0
Video encoder N/A VCE 1.0 VCE 2.0 VCE 3.1 N/A VCE 2.0 VCE 3.1
GPU power saving PowerPlay PowerTune PowerPlay PowerTune[39]
TrueAudio N/A  [40] N/A  
FreeSync 1
2
1
2
HDCP[h] ? 1.4 1.4
2.2
? 1.4 1.4
2.2
PlayReady[h] N/A 3.0 not yet N/A 3.0 not yet
Supported displays[i] 2–3 2–4 3 3 (desktop)
4 (mobile, embedded)
4 2 3 4
/drm/radeon[j][42][43]   N/A   N/A
/drm/amdgpu[j][44] N/A  [45]   N/A  [45]  
  1. ^ APU models: A8-7680, A6-7480. CPU only: Athlon X4 845.
  2. ^ A PC would be one node.
  3. ^ An APU combines a CPU and a GPU. Both have cores.
  4. ^ Requires firmware support.
  5. ^ No SSE4. No SSSE3.
  6. ^ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  7. ^ Unified shaders : texture mapping units : render output units
  8. ^ a b To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  9. ^ To feed more than two displays, the additional panels must have native DisplayPort support.[41] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
  10. ^ a b DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

GPUsEdit

The following table shows features of AMD's GPUs (see also: List of AMD graphics processing units).

Name of GPU series Wonder Mach 3D Rage Rage Pro Rage R100 R200 R300 R400 R500 R600 RV670 R700 Evergreen Northern
Islands
Southern
Islands
Sea
Islands
Volcanic
Islands
Arctic
Islands/Polaris
Vega Navi
Released 1986 1991 1996 1997 1998 Apr 2000 Aug 2001 Sep 2002 May 2004 Oct 2005 May 2007 Nov 2007 Jun 2008 Sep 2009 Oct 2010 Jan 2012 Sep 2013 Jun 2015 Jun 2016 Jun 2017 Jul 2019
Marketing Name Wonder Mach 3D Rage Rage Pro Rage Radeon 7000 Radeon 8000 Radeon 9000 Radeon X700/X800 Radeon X1000 Radeon HD 1000/2000 Radeon HD 3000 Radeon HD 4000 Radeon HD 5000 Radeon HD 6000 Radeon HD 7000 Radeon Rx 200 Radeon Rx 300 Radeon RX 400/500 Radeon RX Vega/Radeon VII(7nm) Radeon RX 5000
AMD support    
Kind 2D 3D
Instruction set Not publicly known TeraScale instruction set GCN instruction set RDNA instruction set
Microarchitecture TeraScale 1 TeraScale 2 (VLIW5) TeraScale 3 (VLIW4) GCN 1st gen GCN 2nd gen GCN 3rd gen GCN 4th gen GCN 5th gen RDNA
Type Fixed pipeline[a] Programmable pixel & vertex pipelines Unified shader model
Direct3D N/A 5.0 6.0 7.0 8.1 9.0
11 (9_2)
9.0b
11 (9_2)
9.0c
11 (9_3)
10.0
11 (10_0)
10.1
11 (10_1)
11 (11_0) 11 (11_1)
12 (11_1)
11 (12_0)
12 (12_0)
11 (12_1)
12 (12_1)
Shader model N/A 1.4 2.0+ 2.0b 3.0 4.0 4.1 5.0 5.1 5.1
6.3
6.4
OpenGL N/A 1.1 1.2 1.3 2.0[b] 3.3 4.5 (on Linux + Mesa 3D: 4.2 with FP64 HW support, 3.3 without)[46][47][48][c] 4.6 (on Linux: 4.6 (Mesa 20.0))
Vulkan N/A 1.0
(Win 7+ or Mesa 17+)
1.2 (Adrenalin 20.1, Linux Mesa 20.0)
OpenCL N/A Close to Metal 1.1 1.2 2.0 (Adrenalin driver on Win7+)
(1.2 on Linux, 2.1 with AMD ROCm)
?
HSA N/A   ?
Video decoding ASIC N/A Avivo/UVD UVD+ UVD 2 UVD 2.2 UVD 3 UVD 4 UVD 4.2 UVD 5.0 or 6.0 UVD 6.3 UVD 7[24][d] VCN 2.0[24][d]
Video encoding ASIC N/A VCE 1.0 VCE 2.0 VCE 3.0 or 3.1 VCE 3.4 VCE 4.0[24][d]
Power saving ? PowerPlay PowerTune PowerTune & ZeroCore Power ?
TrueAudio N/A Via dedicated DSP Via shaders
FreeSync N/A 1
2
HDCP[e] ? 1.4 1.4
2.2
1.4
2.2
2.3
PlayReady[e] N/A 3.0   3.0
Supported displays[f] 1–2 2 2–6 ?
Max. resolution ? 2–6 ×
2560×1600
2–6 ×
4096×2160 @ 60 Hz
2–6 ×
5120×2880 @ 60 Hz
3 ×
7680×4320 @ 60 Hz[49]
?
/drm/radeon[g]   N/A
/drm/amdgpu[g] N/A Experimental[50]  
  1. ^ The Radeon 100 Series has programmable pixel shaders, but do not fully comply with DirectX 8 or Pixel Shader 1.0. See article on R100's pixel shaders.
  2. ^ These series do not fully comply with OpenGL 2+ as the hardware does not support all types of non-power of two (NPOT) textures.
  3. ^ OpenGL 4+ compliance requires supporting FP64 shaders and these are emulated on some TeraScale chips using 32-bit hardware.
  4. ^ a b c The UVD and VCE were replaced by the Video Core Next (VCN) ASIC in the Raven Ridge APU implementation of Vega.
  5. ^ a b To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  6. ^ More displays may be supported with native DisplayPort connections, or splitting the maximum resolution between multiple monitors with active converters.
  7. ^ a b DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

Operating system supportEdit

The UVD SIP core needs to be supported by the device driver, which provides one or more interfaces such as VDPAU, VAAPI or DXVA. One of these interfaces is then used by end-user software, for example VLC media player or GStreamer, to access the UVD hardware and make use of it.

AMD Catalyst, AMD's proprietary graphics device driver that supports UVD, is available for Microsoft Windows and some Linux distributions. Additionally, a free device driver is available, which also supports the UVD hardware.

LinuxEdit

 
Linux support for the UVD ASIC is provided by the Linux kernel device driver amdgpu.[51]

Support for UVD has been available in AMD's proprietary driver Catalyst version 8.10 since October 2008 through X-Video Motion Compensation (XvMC) or X-Video Bitstream Acceleration (XvBA).[52][53] Since April 2013,[54] UVD is supported by the free and open-source "radeon" device driver through Video Decode and Presentation API for Unix (VDPAU). An implementation of VDPAU is available as Gallium3D state tracker in Mesa 3D.

On 28 June 2014, Phoronix published some benchmarks on using Unified Video Decoder through the VDPAU interface running MPlayer on Ubuntu 14.04 with version 10.3-testing of Mesa 3D.[55]

WindowsEdit

Microsoft Windows supported UVD since it was launched. UVD currently only supports DXVA (DirectX Video Acceleration) API specification for the Microsoft Windows and Xbox 360 platforms to allow video decoding to be hardware accelerated, thus the media player software also has to support DXVA to be able to utilize UVD hardware acceleration.

OthersEdit

Support for running custom FreeRTOS-based firmware on the Radeon HD 2400's UVD core (based on an Xtensa CPU), interfaced with a STM32 ARM-based board via I2C, was attempted as of January 2012.[56]

Predecessors and SuccessorEdit

PredecessorsEdit

The Video Shader and ATI Avivo are similar technologies incorporated into previous ATI products.

SuccessorEdit

The UVD was succeeded by AMD Video Core Next in the Raven Ridge series of APUs released in October 2017. The VCN combines both encode (VCE) and decode (UVD).[57]

See alsoEdit

NotesEdit

ReferencesEdit

  1. ^ "AMD A-Series APU block diagram". 2011-06-30. Retrieved 2015-01-22.
  2. ^ "Linux operating system on Xtensa processors".
  3. ^ Cheung, Ken (2009-01-08). "Consumer Electronics Show Features Tensilica-enabled Products". EDA Geek. Archived from the original on 2014-04-26. Retrieved 2014-05-15.
  4. ^ "Customer Profiles | Cadence IP". Ip.cadence.com. 2014-04-13. Retrieved 2014-05-15.
  5. ^ "Tensilica News: Excellent AMD ATI Video with Xtensa". tensilica.com. 2009-10-05. Retrieved 2014-05-15.
  6. ^ "ATI Licenses Tensilica's Xtensa Configurable Processor". Business Wire. 2004-10-18. Retrieved 2014-05-15.
  7. ^ "HardSpell review" (in Chinese). Archived from the original on September 27, 2007.
  8. ^ Smith, Ryan (February 24, 2010). "AMD's Radeon HD 5450: The Next Step In HTPC Video Cards". AnandTech. AnandTech, Inc. p. 4. Retrieved April 7, 2010. Since deinterlacing and other AVIVO post-processing actions are done by the shader hardware, the limited shading capabilities of these cards meant that AMD couldn’t offer the full suite of AVIVO abilities at once.
  9. ^ (in Chinese) PC-DVD discussion thread, retrieved August 23, 2008
  10. ^ White Paper | AMD Unified Video Decoder (UVD)
  11. ^ "Archived copy". Archived from the original on 2012-03-20. Retrieved 2013-09-01.CS1 maint: archived copy as title (link) by Jansen Ng, 10/21/2010 DailyTech
  12. ^ "AMD A6-3650 Llano APU Review - Page 5". Hardwarecanucks.com. Retrieved 2014-04-17.
  13. ^ Koen Crijns (14 January 2014). "AMD A10-7850K 'Kaveri' review: AMD's new APU". hardware.info.
  14. ^ Ryan Smith. "GCN 1.2 – Image & Video Processing - AMD Radeon R9 285 Review: Feat. Sapphire R9 285 Dual-X OC". anandtech.com.
  15. ^ "Guide to HEVC_H.265 Encoding and Playback". TechSpot.
  16. ^ "Key features of AMD's third iteration of GCN architecture revealed".
  17. ^ http://lists.freedesktop.org/archives/dri-devel/2015-June/084083.html [pull] amdgpu drm-next-4.2
  18. ^ "Display Matters Virtual Super Resolution, Frame Rate Targeting, and HEVC Decoding - The AMD Radeon R9 Fury X Review Aiming For the Top". Anandtech.
  19. ^ "AMD Radeon R9 Fury X im Test: Eine ernsthafte Alternative zu Nvidias Topmodellen".
  20. ^ Rick Merritt (2015-01-05). "AMD Describes Notebook Processor". EE Times. Retrieved 2015-01-10.
  21. ^ AMD. "Radeon Software Crimson ReLive Edition 16.12.1 Release Notes". amd.com. amd.com. Retrieved 2016-12-29.
  22. ^ "AMD Introduces New Professional Graphics Vision and Strategy, Empowering the "Art of the Impossible"". AMD.
  23. ^ "AMD Launches the Radeon Rebellion with the Radeon™ RX 480 Graphics Card, Available Now". AMD.
  24. ^ a b c d Killian, Zak (22 March 2017). "AMD publishes patches for Vega support on Linux". Tech Report. Retrieved 23 March 2017.
  25. ^ Larabel, Michael (20 March 2017). "AMD Sends Out 100 Patches, Enabling Vega Support In AMDGPU DRM". Phoronix. Retrieved 25 August 2017.
  26. ^ http://radeon.com/_downloads/vega-whitepaper-11.6.17.pdf
  27. ^ Deucher, Alex (2018-05-15). "[PATCH 50/57] drm/amdgpu/vg20:Enable the 2nd instance IRQ for uvd 7.2". Retrieved 2019-01-13.
  28. ^ Deucher, Alex (2018-05-15). "[PATCH 42/57] drm/amd/include/vg20: adjust VCE_BASE to reuse vce 4.0 header files". Retrieved 2019-01-13.
  29. ^ a b c "X.Org: Radeon Feature Matrix – Video Core Next".
  30. ^ a b "X.Org: Radeon Feature Matrix – Unified Video Decoder".
  31. ^ HKEPC Hardware. "電腦領域 HKEPC Hardware - 全港 No.1 PC網站". hkepc.com. Archived from the original on 2007-03-12.
  32. ^ "DailyTech - Whoops, ATI Radeon HD 2900 XT Lacks UVD". dailytech.com. Archived from the original on 2013-12-24.
  33. ^ "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
  34. ^ "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
  35. ^ "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
  36. ^ a b "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
  37. ^ Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
  38. ^ Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
  39. ^ Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
  40. ^ "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
  41. ^ "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
  42. ^ Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.
  43. ^ "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.
  44. ^ Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
  45. ^ a b Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.
  46. ^ "AMD Radeon Software Crimson Edition Beta". AMD. Retrieved 2018-04-20.
  47. ^ "Mesamatrix". mesamatrix.net. Retrieved 2018-04-22.
  48. ^ "RadeonFeature". X.Org Foundation. Retrieved 2018-04-20.
  49. ^ "Radeon's next-generation Vega architecture" (PDF). Radeon Technologies Group (AMD). Archived from the original (PDF) on 2018-09-06. Retrieved 13 June 2017.
  50. ^ Larabel, Michael (7 December 2016). "The Best Features of the Linux 4.9 Kernel". Phoronix. Retrieved 7 December 2016.
  51. ^ Michael Larabel (October 8, 2014). "The Slides Announcing The New "AMDGPU" Kernel Driver". Phoronix. Retrieved January 22, 2015.
  52. ^ "UVD Is Enabled For Linux In Catalyst 8.10". Phoronix. 2008-10-15. Retrieved 2015-01-22.
  53. ^ "AMD's X-Video Bitstream Acceleration". Phoronix. 2008-10-28. Retrieved 2015-01-22.
  54. ^ "AMD Releases Open-Source UVD Video Support". Phoronix. 2013-04-02. Retrieved 2015-01-22.
  55. ^ "AMD Radeon VDPAU Video Performance With Gallium3D". Phoronix. 2014-06-28. Retrieved 2015-01-22.
  56. ^ "Interfacing a PC graphics card (Radeon HD 2400) with a STM32 microcontroller". Edaboard.com. 2012-01-09. Retrieved 2014-04-27.
  57. ^ Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands In Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.

External linksEdit