Transient execution CPU vulnerability
Transient execution CPU vulnerabilities are vulnerabilities in a computer system in which a speculative execution optimization implemented in a microprocessor is exploited to leak secret data to an unauthorized party. The classic example is Spectre that gave its name to this kind of side-channel attack, but since January 2018 many different vulnerabilities have been identified.
Modern computers are highly parallel devices, composed of components with very different performance characteristics. If an operation (such as a branch) cannot yet be performed because some earlier slow operation (such as a memory read) has not yet completed, a microprocessor may attempt to predict the result of the earlier operation and execute the later operation speculatively, acting as if the prediction was correct. The prediction may be based on recent behavior of the system. When the earlier, slower operation completes, the microprocessor determines whether prediction was correct or incorrect. If it was correct then execution proceeds uninterrupted; if it was incorrect then the microprocessor rolls back the speculatively executed operations and repeats the original instruction with the real result of the slow operation. Specifically, a transient instruction refers to an instruction processed by error by the processor (incriminating the branch predictor in the case of Spectre) which can affect the micro-architectural state of the processor, leaving the architectural state without any trace of its execution.
In terms of the directly visible behavior of the computer it is as if the speculatively executed code "never happened". However, this speculative execution may affect the state of certain components of the microprocessor, such as the cache, and this effect may be discovered by careful monitoring of the timing of subsequent operations.
If an attacker can arrange that the speculatively executed code (which may be directly written by the attacker, or may be a suitable gadget that they have found in the targeted system) operates on secret data that they are unauthorized to access, and has a different effect on the cache for different values of the secret data, they may be able to discover the value of the secret data.
Starting in 2017, multiple examples of such vulnerabilities were identified, with publication starting in early 2018.
Vulnerabilities and mitigations summaryEdit
|Mitigation Type||Comprehensiveness||Effectiveness||Performance Impact|
|Firmware Microcode Update||Partial||Partial…Full||None…Large|
Hardware mitigations require change to the CPU design and thus a new iteration of hardware, but impose close to zero performance loss. Microcode updates alter the software that the CPU runs on, requiring patches to be released and integrated into every operating system and for each CPU. OS/VMM mitigations are applied at the operating system or virtual machine level and (depending on workload) often incur quite a significant performance loss. Software recompilation requires recompiling every piece of software and usually incur a severe performance hit.
|CVE||Affected CPU architectures and mitigations|
|Ice Lake||Cascade Lake,
|Zen 1 / Zen 1+||Zen 2|
Bounds Check Bypass
|2017-5753||Software Recompilation||Software Recompilation|
Branch Target Injection
|2017-5715||Hardware + OS||Microcode + OS||Microcode + OS||Microcode + OS/VMM||Hardware + OS/VMM|
|SpectreRSB/ret2spec Return Mispredict||2018-15572||OS|
Rogue Data Cache Load
|2017-5754||Not affected||Microcode||Not affected|
|Spectre-NG v3a||2018-3640||Not affected||Microcode|
Speculative Store Bypass
|2018-3639||Hardware + OS/VMM||Microcode + OS||OS/VMM||Hardware + OS/VMM|
L1 Terminal Fault, L1TF
|2018-3615||Not affected||Microcode||Not affected|
Lazy FP State Restore
Bounds Check Bypass Store
Read-only Protection Bypass (RPB)
|No CVE and has never been confirmed by Intel||Not affected|
L1 Terminal Fault (L1TF)
|2018-3620||Not affected||Microcode + OS||Not affected|
L1 Terminal Fault (L1TF)
Microarchitectural Fill Buffer Data Sampling (MFBDS)
Microarchitectural Load Port Data Sampling (MLPDS)
|2018-12127||Not affected||Not affected ||Not affected||Microcode + OS|
Microarchitectural Data Sampling Uncacheable Memory (MDSUM)
|2019-11091||Not affected||Microcode + OS|
Microarchitectural Store Buffer Data Sampling (MSBDS)
|2018-12126||Microcode||Not affected ||Not affected||Microcode + OS|
|Spectre SWAPGS||2019-1125||Same as Spectre 1|
Transactional Asynchronous Abort (TAA)
|2019-11135||Not Affected||Microcode + OS|
L1D Eviction Sampling (L1DES)
Vector Register Sampling (VRS)
|Load Value Injection (LVI)||2020-0551||Software recompilation|
|Take a Way||Not affected||Not fixed yet (disputed)|
Special Register Buffer Data Sampling (SRBDS)
|2020-0543||Not affected||Microcode||Not affected|
|Blindside||Affected, not fixed yet|
The 8th generation Coffee Lake architecture in this table also applies to a wide range of previously released Intel CPUs, not limited to the architectures based on Intel Core, Pentium 4 and Intel Atom starting with Silvermont. Various CPU microarchitectures not included above are also affected, among them are IBM Power, ARM, MIPS and others.
Spectre class vulnerabilities will remain unfixed because otherwise CPU designers will have to disable OoOE which will entail a massive performance loss.
- 1.^ Stepping 5 of the 2nd Generation Intel® Xeon® Scalable Processors based on Cascade Lake microarchitecture is affected by both MSBDS and MLPDS.
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- "Take A Way: Exploring the Security Implications of AMD'sCache Way Predictors" (PDF).
- March 2020, Paul Alcorn 07. "New AMD Side Channel Attacks Discovered, Impacts Zen Architecture". Tom's Hardware. Retrieved 2020-03-07.
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- "Deep Dive: Special Register Buffer Data Sampling". software.intel.com. Retrieved 2020-06-09.
- "INTEL-SA-00320". Intel. Retrieved 2020-06-09.
- "Don't be BlindSided: Watch speculative memory probing bypass kernel defenses, give malware root control". www.theregister.com. Retrieved 2020-09-11.
- "BlindSide". VUSec. Retrieved 2020-09-11.
- "INTEL-SA-00088". Intel. Retrieved 2018-09-01.
- "INTEL-SA-00115". Intel. Retrieved 2018-09-01.
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- "Potential Impact on Processors in the POWER Family". IBM PSIRT Blog. 2019-05-14. Retrieved 2019-09-29.
- Vulnerabilities associated with CPU speculative execution
- A systematic evaluation of transient execution attacks and defenses
- A dynamic tree of transient execution vulnerabilities for Intel, AMD and ARM CPUs
- Transient Execution Attacks by Daniel Gruss, June 20, 2019
- CPU Bugs
- Intel: Refined Speculative Execution Terminology