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In integrated circuits, the stepping level or revision level is a version number that refers to the introduction or revision of one or more photolithographic photomasks within the set of photomasks that is used to pattern an integrated circuit. The term originated from the name of the equipment ("steppers") that exposes the photoresist to light. Integrated circuits have two primary classes of mask sets: firstly, "base" layers that are used to build the structures, such as transistors, that comprise circuit logic and, secondly, "metal" layers that connect the circuit logic.
Typically, when an integrated circuit manufacturer such as Intel or AMD produces a new stepping (i.e. a revision to the masks), it is because it has found bugs in the logic, has made improvements to the design that permit faster processing, has found a way to increase yield or improve the "bin splits" (i.e. create faster transistors and thus faster CPUs), has improved manoeuvrability to more easily identify marginal circuits, or has reduced the circuit testing time, which can in turn reduce the cost of testing.
Many integrated circuits allow interrogation to reveal information about their features, including stepping level. For example, executing CPUID instruction with the EAX register set to '1' on x86 CPUs will result in values being placed in other registers that show the CPU's stepping level.
Stepping identifiers commonly comprise a letter followed by a number, for example B2. Usually, the letter indicates the revision level of a CPU's base layers and the number indicates the revision level of the metal layers. A change of letter indicates a change to both the base layer mask revision and metal layers whereas a change in the number indicates a change in the metal layer mask revision only. This is analogous to the major/minor revision numbers in software versioning. Base layer revision changes are time consuming and more expensive for the manufacturer, but some fixes are difficult or impossible to accomplish with metal-only changes.
The Intel Core microarchitecture uses a number of steppings, which unlike prior microarchitectures not only represent incremental improvements but also changes to features, such as a different cache size or the addition of low-power modes. Most of these steppings are used across brands, typically involving features being disabled or clock frequencies being reduced on low-end chips. Steppings with a reduced cache size use a separate naming scheme, which means that CPU steppings are not necessarily released in alphabetic order of stepping.
- "From Sand to Silicon "Making of a Chip" Illustrations" (PDF). Intel. May 2009. Retrieved July 25, 2014.
- Seth P. Bates (2000). "Silicon Wafer Processing" (PDF). gatech.edu. Archived from the original (PDF) on 2015-06-16. Retrieved July 25, 2014.
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