In computing, especially digital signal processing, the multiply–accumulate operation is a common step that computes the product of two numbers and adds that product to an accumulator. The hardware unit that performs the operation is known as a multiplier–accumulator (MAC, or MAC unit); the operation itself is also often called a MAC or a MAC operation. The MAC operation modifies an accumulator a:
When done with floating point numbers, it might be performed with two roundings (typical in many DSPs), or with a single rounding. When performed with a single rounding, it is called a fused multiply–add (FMA) or fused multiply–accumulate (FMAC).
Modern computers may contain a dedicated MAC, consisting of a multiplier implemented in combinational logic followed by an adder and an accumulator register that stores the result. The output of the register is fed back to one input of the adder, so that on each clock cycle, the output of the multiplier is added to the register. Combinational multipliers require a large amount of logic, but can compute a product much more quickly than the method of shifting and adding typical of earlier computers. Percy Ludgate was the first to conceive a MAC in his Analytical Machine of 1909, and the first to exploit a MAC for division (using multiplication seeded by reciprocal, via the convergent series (1+x)−1). The first modern processors to be equipped with MAC units were digital signal processors, but the technique is now also common in general-purpose processors.
In floating-point arithmeticEdit
When done with integers, the operation is typically exact (computed modulo some power of two). However, floating-point numbers have only a certain amount of mathematical precision. That is, digital floating-point arithmetic is generally not associative or distributive. (See Floating point § Accuracy problems.) Therefore, it makes a difference to the result whether the multiply–add is performed with two roundings, or in one operation with a single rounding (a fused multiply–add). IEEE 754-2008 specifies that it must be performed with one rounding, yielding a more accurate result.
A fused multiply–add (sometimes known as FMA or fmadd) is a floating-point multiply–add operation performed in one step, with a single rounding. That is, where an unfused multiply–add would compute the product b×c, round it to N significant bits, add the result to a, and round back to N significant bits, a fused multiply–add would compute the entire expression a+b×c to its full precision before rounding the final result down to N significant bits.
A fast FMA can speed up and improve the accuracy of many computations that involve the accumulation of products:
- Dot product
- Matrix multiplication
- Polynomial evaluation (e.g., with Horner's rule)
- Newton's method for evaluating functions (from the inverse function)
- Convolutions and artificial neural networks
Fused multiply–add can usually be relied on to give more accurate results. However, William Kahan has pointed out that it can give problems if used unthinkingly. If x2 − y2 is evaluated as ((x×x) − y×y) using fused multiply–add, then the result may be negative even when x = y due to the first multiplication discarding low significance bits. This could then lead to an error if, for instance, the square root of the result is then evaluated.
When implemented inside a microprocessor, an FMA can actually be faster than a multiply operation followed by an add. However, standard industrial implementations based on the original IBM RS/6000 design require a 2N-bit adder to compute the sum properly.
A useful benefit of including this instruction is that it allows an efficient software implementation of division (see division algorithm) and square root (see methods of computing square roots) operations, thus eliminating the need for dedicated hardware for those operations.
Dot product instructionEdit
Some machines combine multiple fused multiply add operations into a single step, e.g. performing a four-element dot-product on two 128-bit SIMD registers a0×b0+a1×b1+a2×b2+a3×b3 with single cycle throughput.
The FMA operation is included in IEEE 754-2008.
The DEC VAX's POLY instruction is used for evaluating polynomials with Horner's rule using a succession of multiply and add steps. Instruction descriptions do not specify whether the multiply and add are performed using a single fma step. This instruction has been a part of the VAX instruction set since its original 11/780 implementation in 1977.
- HP PA-8000 (1996) and above
- Hitachi SuperH SH-4 (1998)
- SCE-Toshiba Emotion Engine (1999)
- Intel Itanium (2001)
- STI Cell (2006)
- Fujitsu SPARC64 VI (2007) and above
- (MIPS-compatible) Loongson-2F (2008)
- Elbrus-8SV (2018)
- x86 processors with FMA3 and/or FMA4 instruction set
- ARM processors with VFPv4 and/or NEONv2:
- GPUs and GPGPU boards:
- Advanced Micro Devices GPUs (2009) and newer
- NVidia GPUs (2010) and newer
- Intel GPUs since Sandy Bridge
- Intel MIC (2012)
- ARM Mali T600 Series (2012) and above
- Vector Processors:
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