A double-gate FinFET device

A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double gate structure. These devices have been given the generic name "finfets" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than the mainstream CMOS technology.

FinFET is a type of non-planar transistor, or "3D" transistor.[1] It is the basis for modern nanoelectronic semiconductor device fabrication. Microchips utilizing FinFET gates first became commercialized in the first half of the 2010s, and became the dominant gate design at 14 nm, 10 nm and 7 nm process nodes.



A planar double-gate MOSFET (DGMOS) transistor was first demonstrated in 1984 by Electrotechnical Laboratory researchers Toshihiro Sekigawa and Yutaka Hayashi, who called it the "XMOS" transistor. They proposed that short-channel effects can be significantly reduced by sandwiching a fully depleted SOI device between two gate electrodes connected together.[2][3]

The first finfet transistor type was called a "Depleted Lean-channel Transistor" or "DELTA" transistor, which was first fabricated by Hitachi Central Research Laboratory's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989.[2][4][5][6] The gate of the transistor can cover and electrically contact the semiconductor channel fin on both the top and the sides or only on the sides. The former is called a tri-gate transistor and the latter a double-gate transistor. A double-gate transistor optionally can have each side connected to two different terminal or contacts. This variant is called split transistor. This enables more refined control of the operation of the transistor.

In 1996, Effendi Leobandung and Stephen Y. Chou from University of Minnesota published a paper at 54th Device Research Conference outlining the benefit of cutting wide CMOS transistor into many channels with narrow width to improve device scaling and increase device current by increasing the effective device width. [7] This structure is what modern FINFET looks like. Even though some device width is scarified by cutting it into narrow widths, the conduction of the side wall of narrow fins more than make up for the loss, for tall fins. [8]

The potential of Digh Hisamoto's research on DELTA transistors drew the attention of the Defense Advanced Research Projects Agency (DARPA), which in 1997 awarded a contract to a research group at UC Berkeley to develop a deep sub-micron transistor based on DELTA technology.[6] The group consisted of Hisamoto along with TSMC's Chenming Hu and other UC Berkeley researchers including Tsu-Jae King Liu, Jeffrey Bokor, Hideki Takeuchi, K. Asano, Jakub Kedziersk, Xuejue Huang, Leland Chang, Nick Lindert, Shibly Ahmed, Cyrus Tabery, Yang‐Kyu Choi, Pushkar Ranade, Sriram Balasubramanian, A. Agarwal and M. Ameen. In 1998, the team developed the first N-channel FinFETs and successfully fabricated devices down to a 17 nm process. The following year, they developed the first P-channel FinFETs.[9] They coined the term "FinFET" (fin field-effect transistor) in a December 2000 paper,[10] with the term used to describe a non-planar, double-gate transistor built on an SOI substrate.[11] In 2001, they developed a 15 nm FinFET process. In 2002, a team including Yu, Chang, Ahmed, Tabery, Hu, Liu and Bokor described a 10 nm process. In 2004, they developed a High-κ/metal gate FinFET.[9]

In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device, based on FinFET technology.[12][13] In 2011, Rice University researchers Masoud Rostami and Kartik Mohanram demonstrated that FINFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates.[14]


The industry's first 25 nanometer transistor operating on just 0.7 volt was demonstrated in December 2002 by TSMC. The "Omega FinFET" design, named after the similarity between the Greek letter "Omega" and the shape in which the gate wraps around the source/drain structure, has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type.

In 2004, Samsung demonstrated a "Bulk FinFET" design, which made it possible to mass-produce FinFET devices. They demonstrated dynamic random-access memory (DRAM) manufactured with a 90 nm Bulk FinFET process.[9]

In 2011, Intel demonstrated tri-gate transistors, where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors.[15][16][17]

Commercially produced chips at 22 nm and below have utilised FinFET gate designs. Intel's "Tri-Gate" variant were announced at 22nm in 2011 for its Ivy Bridge microarchitecture.[18] These devices shipped from 2012 onwards. From 2014 onwards, at 14 nm (or 16 nm) major foundries (TSMC, Samsung, GlobalFoundries) utilised FinFET designs.

In 2013, SK Hynix began commercial mass-production of a 16 nm process,[19] TSMC began production of a 16 nm FinFET process,[20] and Samsung Electronics began production of a 10 nm process.[21] TSMC began production of a 7 nm process in 2017,[22] and Samsung began production of a 5 nm process in 2018.[23] In 2019, Samsung announced plans for the commercial production of a 3 nm GAAFET process by 2021.[24]

Commercial production of nanoelectronic FinFET semiconductor memory began in the 2010s. In 2013, SK Hynix began mass-production of 16 nm NAND flash memory,[19] and Samsung Electronics began production of 10 nm multi-level cell (MLC) NAND flash memory.[21] In 2017, TSMC began production of SRAM memory using a 7 nm process.[22]

See alsoEdit


  1. ^ "What is Finfet?". Computer Hope. April 26, 2017. Retrieved 4 July 2019.
  2. ^ a b Colinge, J.P. (2008). FinFETs and Other Multi-Gate Transistors. Springer Science & Business Media. p. 11. ISBN 9780387717517.
  3. ^ Sekigawa, Toshihiro; Hayashi, Yutaka (1 August 1984). "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate". Solid-State Electronics. 27 (8): 827–828. Bibcode:1984SSEle..27..827S. doi:10.1016/0038-1101(84)90036-4. ISSN 0038-1101.
  4. ^ Hisamoto, D.; Kaga, T.; Kawamoto, Y.; Takeda, E. (December 1989). "A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET". International Technical Digest on Electron Devices Meeting: 833–836. doi:10.1109/IEDM.1989.74182.
  5. ^ "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Retrieved 4 July 2019.
  6. ^ a b "The Breakthrough Advantage for FPGAs with Tri-Gate Technology" (PDF). Intel. 2014. Retrieved 4 July 2019.
  7. ^ Leobandung, Effendi (24 June 1996). "Reduction of Short Channel Effects in SO1 MOSFETs with 35 nm Channel Width and 70 nm Channel Length". 54th Device Research Conference Digest.
  8. ^ Leobandung, Effendi (June 1996). Nanoscale MOSFETs and single charge transistors on SOI. Minneapolis, MN: U of Minnesota, Ph.D. Thesis. p. 72.
  9. ^ a b c Tsu‐Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Retrieved 9 July 2019.
  10. ^ Hisamoto, Digh; Hu, Chenming; Bokor, J.; King, Tsu-Jae; Anderson, E.; et al. (December 2000). "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm". IEEE Transactions on Electron Devices. 47 (12): 2320–2325. Bibcode:2000ITED...47.2320H. CiteSeerX doi:10.1109/16.887014.
  11. ^ Hisamoto, Digh; Hu, Chenming; Huang, Xuejue; Lee, Wen-Chin; Kuo, C.; et al. (May 2001). "Sub-50 nm P-channel FinFET" (PDF). IEEE Transactions on Electron Devices. 48 (5): 880–886. Bibcode:2001ITED...48..880H. doi:10.1109/16.918235.
  12. ^ "Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012
  13. ^ Lee, Hyunjin; et al. (2006), "Sub-5nm All-Around Gate FinFET for Ultimate Scaling", Symposium on VLSI Technology, 2006: 58–59, doi:10.1109/VLSIT.2006.1705215, hdl:10203/698, ISBN 978-1-4244-0005-8
  14. ^ Rostami, M.; Mohanram, K. (2011). "IEEE Xplore Abstract - Dual- Independent-Gate FinFETs for Low Power Logic Circuits". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30 (3): 337–349. doi:10.1109/TCAD.2010.2097310. hdl:1911/72088.
  15. ^ Bohr, Mark; Mistry, Kaizad (May 2011). "Intel's Revolutionary 22 nm Transistor Technology" (PDF). intel.com. Retrieved April 18, 2018.
  16. ^ Grabham, Dan (May 6, 2011). "Intel's Tri-Gate transistors: everything you need to know". TechRadar. Retrieved April 19, 2018.
  17. ^ Bohr, Mark T.; Young, Ian A. (2017). "CMOS Scaling Trends and Beyond". IEEE Micro. 37 (6): 20–29. doi:10.1109/MM.2017.4241347. The next major transistor innovation was the introduction of FinFET (tri-gate) transistors on Intel’s 22-nm technology in 2011.
  18. ^ Intel 22nm 3-D Tri-Gate Transistor Technology
  19. ^ a b "History: 2010s". SK Hynix. Retrieved 8 July 2019.
  20. ^ "16/12nm Technology". TSMC. Retrieved 30 June 2019.
  21. ^ a b "Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware. 11 April 2013. Retrieved 21 June 2019.
  22. ^ a b "7nm Technology". TSMC. Retrieved 30 June 2019.
  23. ^ Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". www.anandtech.com. Retrieved 2019-05-31.
  24. ^ Armasu, Lucian (11 January 2019), "Samsung Plans Mass Production of 3nm GAAFET Chips in 2021", www.tomshardware.com