A fin field-effect transistor (FinFET) is a multigate device, a MOSFET (metal-oxide-semiconductor field-effect transistor) built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double gate structure. These devices have been given the generic name "finfets" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than the mainstream CMOS technology.
FinFET is a type of non-planar transistor, or "3D" transistor. It is the basis for modern nanoelectronic semiconductor device fabrication. Microchips utilizing FinFET gates first became commercialized in the first half of the 2010s, and became the dominant gate design at 14 nm, 10 nm and 7 nm process nodes.
A planar double-gate MOSFET (DGMOS) transistor was first demonstrated in 1984 by Electrotechnical Laboratory researchers Toshihiro Sekigawa and Yutaka Hayashi, who called it the "XMOS" transistor. They proposed that short-channel effects can be significantly reduced by sandwiching a fully depleted SOI device between two gate electrodes connected together.
The first finfet transistor type was called a "Depleted Lean-channel Transistor" or "DELTA" transistor, which was first fabricated by Hitachi Central Research Laboratory's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989. The gate of the transistor can cover and electrically contact the semiconductor channel fin on both the top and the sides or only on the sides. The former is called a tri-gate transistor and the latter a double-gate transistor. A double-gate transistor optionally can have each side connected to two different terminal or contacts. This variant is called split transistor. This enables more refined control of the operation of the transistor.
In 1996, Effendi Leobandung and Stephen Y. Chou from University of Minnesota published a paper at 54th Device Research Conference outlining the benefit of cutting wide CMOS transistor into many channels with narrow width to improve device scaling and increase device current by increasing the effective device width.  This structure is what modern FINFET looks like. Even though some device width is scarified by cutting it into narrow widths, the conduction of the side wall of narrow fins more than make up for the loss, for tall fins. 
The potential of Digh Hisamoto's research on DELTA transistors drew the attention of the Defense Advanced Research Projects Agency (DARPA), which in 1997 awarded a contract to a research group at UC Berkeley to develop a deep sub-micron transistor based on DELTA technology. The group consisted of Hisamoto along with TSMC's Chenming Hu and other UC Berkeley researchers including Tsu-Jae King Liu, Jeffrey Bokor, Hideki Takeuchi, K. Asano, Jakub Kedziersk, Xuejue Huang, Leland Chang, Nick Lindert, Shibly Ahmed, Cyrus Tabery, Yang‐Kyu Choi, Pushkar Ranade, Sriram Balasubramanian, A. Agarwal and M. Ameen. In 1998, the team developed the first N-channel FinFETs and successfully fabricated devices down to a 17 nm process. The following year, they developed the first P-channel FinFETs. They coined the term "FinFET" (fin field-effect transistor) in a December 2000 paper, with the term used to describe a non-planar, double-gate transistor built on an SOI substrate. In 2001, they developed a 15 nm FinFET process. In 2002, a team including Yu, Chang, Ahmed, Tabery, Hu, Liu and Bokor described a 10 nm process. In 2004, they developed a High-κ/metal gate FinFET.
In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device, based on FinFET technology. In 2011, Rice University researchers Masoud Rostami and Kartik Mohanram demonstrated that FINFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates.
The industry's first 25 nanometer transistor operating on just 0.7 volt was demonstrated in December 2002 by TSMC. The "Omega FinFET" design, named after the similarity between the Greek letter "Omega" and the shape in which the gate wraps around the source/drain structure, has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type.
In 2004, Samsung demonstrated a "Bulk FinFET" design, which made it possible to mass-produce FinFET devices. They demonstrated dynamic random-access memory (DRAM) manufactured with a 90 nm Bulk FinFET process.
In 2011, Intel demonstrated tri-gate transistors, where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors.
Commercially produced chips at 22 nm and below have utilised FinFET gate designs. Intel's "Tri-Gate" variant were announced at 22nm in 2011 for its Ivy Bridge microarchitecture. These devices shipped from 2012 onwards. From 2014 onwards, at 14 nm (or 16 nm) major foundries (TSMC, Samsung, GlobalFoundries) utilised FinFET designs.
In 2013, SK Hynix began commercial mass-production of a 16 nm process, TSMC began production of a 16 nm FinFET process, and Samsung Electronics began production of a 10 nm process. TSMC began production of a 7 nm process in 2017, and Samsung began production of a 5 nm process in 2018. In 2019, Samsung announced plans for the commercial production of a 3 nm GAAFET process by 2021.
Commercial production of nanoelectronic FinFET semiconductor memory began in the 2010s. In 2013, SK Hynix began mass-production of 16 nm NAND flash memory, and Samsung Electronics began production of 10 nm multi-level cell (MLC) NAND flash memory. In 2017, TSMC began production of SRAM memory using a 7 nm process.
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The next major transistor innovation was the introduction of FinFET (tri-gate) transistors on Intel’s 22-nm technology in 2011.
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