# Dual impedance

Dual impedance and dual network are terms used in electronic network analysis. The dual of an impedance is its reciprocal, or algebraic inverse . For this reason the **dual impedance** is also called the inverse impedance. Another way of stating this is that the dual of is the admittance .

The dual of a network is the network whose impedances are the duals of the original impedances. In the case of a black-box network with multiple ports, the impedance looking into each port must be the dual of the impedance of the corresponding port of the dual network.

This is consistent with the general notion duality of electric circuits, where the voltage and current are interchanged, etc., since yields ^{[1]}

*Parts of this article or section rely on the reader's knowledge of the complex impedance representation of capacitors and inductors and on knowledge of the frequency domain representation of signals*.

## Scaled and normalised dualsEdit

In physical units, the dual is taken with respect to some nominal or characteristic impedance. To do this, Z and Z' are scaled to the nominal impedance Z_{0} so that

Z_{0} is usually taken to be a purely real number R_{0}, so Z' is changed by a real factor of R_{0}^{2}. In other words, the dual circuit is qualitatively the same circuit but all the component values are scaled by R_{0}^{2}.^{[2]} The scaling factor R_{0}^{2} has the dimensions of Ω^{2}, so the constant 1 in the unitless expression would actually be assigned the dimensions Ω^{2} in a dimensional analysis.

## Duals of basic circuit elementsEdit

Element | Z | Dual | Z' |
---|---|---|---|

(Parallel sum) |
|||

## Graphical methodEdit

There is a graphical method of obtaining the dual of a network which is often easier to use than the mathematical expression for the impedance. Starting with a circuit diagram of the network in question, Z, the following steps are drawn on the diagram to produce Z' superimposed on top of Z. Typically, Z' will be drawn in a different colour to help distinguish it from the original, or, if using computer-aided design, Z' can be drawn on a different layer.

- A generator is connected to each port of the original network. The purpose of this step is to prevent the ports from being "lost" in the inversion process. This happens because a port left open circuit will transform into a short circuit and disappear.
- A dot is drawn at the centre of each mesh of the network Z. These dots will become the circuit nodes of Z'.
- A conductor is drawn which entirely encloses the network Z. This conductor also becomes a node of Z'.
- For each circuit element of Z, its dual is drawn between the nodes in the centre of the meshes either side of Z. Where Z is on the edge of the network, one of these nodes will be the enclosing conductor from the previous step.
^{[4]}

This completes the drawing of Z'. This method also serves to demonstrate that the dual of a mesh transforms into a node and the dual of a node transforms into a mesh. Two examples are given below.

### Example: star networkEdit

It is now clear that the dual of a star network of inductors is a delta network of capacitors. This dual circuit is not the same thing as a star-delta (Y-Δ) transformation. A Y-Δ transform results in an *equivalent* circuit, not a dual circuit.

### Example: Cauer networkEdit

Filters designed using Cauer's topology of the first form are low-pass filters consisting of a ladder network of series inductors and shunt capacitors.

It can now be seen that the dual of a Cauer low-pass filter is still a Cauer low-pass filter. It does not transform into a high-pass filter as might have been expected. Note, however, that the first element is now a shunt component instead of a series component.

## See alsoEdit

## ReferencesEdit

## BibliographyEdit

*Redifon Radio Diary, 1970*, pp. 45–48, William Collins Sons & Co, 1969.- Ghosh, Smarajit,
*Network Theory: Analysis and Synthesis*, Prentice Hall of India - Guillemin, Ernst A.,
*Introductory Circuit Theory*, New York: John Wiley & Sons, 1953 OCLC 535111 - Suresh, Kumar K. S., "Introduction to network topology" chapter 11 in
*Electric Circuits And Networks*, Pearson Education India, 2010 ISBN 81-317-5511-8.