The ARM Cortex-A55 is a microarchitecture implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A55 is a 2-wide decode in-order superscalar pipeline.
|Designed by||ARM Holdings|
|L1 cache||32–128 KB (16–64 KB I-cache with parity, 16–64 KB D-cache) per core|
|L2 cache||64–256 KB|
|L3 cache||512 KB – 4 MB|
|Architecture and classification|
|Products, models, variants|
|Product code name(s)|
The Cortex-A55 serves as the successor of the ARM Cortex-A53, designed to improve performance and energy efficiency over the A53. ARM has stated the A55 should have 15% improved power efficiency and 18% increased performance relative to the A53. Memory access and branch prediction are also improved relative to the A53.
The Cortex-A75 and Cortex-A55 cores are the first products to support ARM's DynamIQ technology. The successor to big.LITTLE, this technology is designed to be more flexible and scalable when designing multi-core products.
The Cortex-A55 is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
ARM has also collaborated with Qualcomm for a semi-custom version of the Cortex-A55, used within the Kryo 385 CPU core. This semi-custom core is also used in some Qualcomm's mid-range SoCs as Kryo 360 Silver and Kryo 460 Silver.
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